Mask ROMs with NOR-type memory cell arrays has been disclosed in Symposium on VLSI Circuit on August 1988, entitled 16 Mb ROM Design Using Bank Select Architecture, pp.85-88, in which bit lines are constructed in a hierarchical arrangement. In the technique of the article, the reading-out process is accomplished through three steps: (a) precharging main bit lines into predetermined voltage levels; (b) sensing a voltage level of a main bit line to determine whether a selected memory cell is an on-cell or an off-cell; and (c) outputting data detected from the selected memory cell to the output of the memory device. Each of the banks has bank selection transistors which connect memory cells to bit lines and ground lines.
In a typical architecture of the mask ROM, bank selection transistors are controlled by bank selection lines and ground selection lines. These are arranged between the memory banks, which take up space. It is desired to find arrangements that save space so that the memory can become more compact.